1. Field of the Invention
This invention is related to initializing registers in various integrated circuits in a system during a boot of the system.
2. Description of the Related Art
Generally, a computer system may include one or more processors, various integrated circuits, and other devices. When the computer system is powered on, the computer system is reset, thus providing an initial state of the computer system. Then, a boot code sequence is executed on a processor of the computer system to determine the resources of the computer system (e.g. memory, disk drives, keyboard, mouse, etc.), perform various checks on the resources, and enable the resources in the computer system so that operating system software can be loaded from disk and executed. The boot code sequence may also create various data structures to be used by the operating system software. The boot code sequence is typically stored in a nonvolatile memory (e.g. a read only memory (ROM) or a flash memory), so that the code can be fetched by the processor and executed before most computer system resources are enabled for use. In personal computer (PC) systems, the boot code sequence is referred to as Basic Input/Output System (BIOS) code. As used herein, a boot code sequence may include any code executed in response to powering on a computer system, to initialize the computer system for executing the operating system (and any desired application programs). The boot code sequence may also be executed in response to resets of the computer system (e.g. warm resets that may occur after the power-on, or cold, reset occurs).
Boot code, such as BIOS code, may include power on self test (POST) code, which may test various resources in the computer system and may initialize the various resources for use. In particular, the computer system may include various integrated circuits (e.g. processors, chipset components such as the north bridge and south bridge components, etc.). Each integrated circuit may require initialization, including writing initial values into various registers in the integrated circuits. The POST code may perform these initializations.
Typically, the integrated circuits included in a given system are developed by one or more integrated circuit vendors. The boot code sequence (e.g. BIOS code) for the given system is developed by a BIOS vendor. There are several BIOS vendors (e.g. Phoenix, Award, and American Megatrends, Inc. (AMI) are the most typical ones). Furthermore, various OEMs may modify the BIOS code from one of the BIOS vendors. Some OEMs (e.g. International Business Machines (IBM)) develop their own custom BIOS code. Other OEMs (e.g. Hewlett-Packard (HP)) may develop their own custom BIOS code for some systems (e.g. high end servers) while using BIOS code from one of the typical BIOS vendors for other systems. Accordingly, the integrated circuit vendors typically provide documentation of the registers in the integrated circuit, and the values to which the registers are to be initialized by the BIOS code. At an early point in the development process, the integrated circuit vendors may provide the documentation to the BIOS vendors to permit concurrent development of the BIOS code.
During the ensuing development of the integrated circuits, there may be multiple revisions of the integrated circuit before the integrated circuit reaches production quality. During the development, the registers that are included in a given integrated circuit may change, the definitions of the contents may change, and the required POST initialization values may change. Frequent updates are supplied to the BIOS vendors in the form of updated documentation, and the updates may also have to be supplied to OEMs as well (if the BIOS vendor has already released BIOS code to OEMs for their customizations).
A prior art POST code sequence for PC systems is illustrated via the flowchart shown in FIG. 1. That is, the flowchart of FIG. 1 may represent one or more instructions which, when executed, perform the functions shown in FIG. 1. FIG. 1 is a high level flowchart of the POST code. The POST code has three phases: early POST (block 10), middle POST (block 12), and late POST (block 14). As used herein, a “phase” is a portion of code in which various defined operations are performed. Various phases may be performed in a defined order. For example, the early POST phase precedes the middle POST phase, which precedes the late POST phase. Each phase is shown in more detail in FIGS. 2-4. That is, the flowcharts of FIGS. 2-4 may each represent one or more instructions in each phase which, when executed, perform the functions shown in FIGS. 2-4, respectively.
FIG. 2 illustrates the early POST phase 10. In the early POST phase 10, the central processing unit (CPU) built-in self-test (BIST) is performed (block 20). An original equipment manufacturer (OEM) hook is then provided (block 22), to permit an OEM to insert custom code for the OEM's system (e.g. to handle the BIST result from the CPU). Generally, a hook is a software mechanism to provide for software expansion. The hook may be implemented in multiple ways. For example, a label may be provided in the code at which the custom code is inserted during compile of the code (e.g. compile of assembly mnemonics to binary code, if the boot code sequence is written in assembly, or compile of higher level language code). Alternatively, the boot code may examine a variable to determine what to do at the hook (e.g. the variable may be the address of the beginning of the custom code). In yet another alternative, the hook may be a call (e.g. a branch) to a predefined address at which the custom code may be located. The variable or predefined address mechanisms may permit the custom code to be used without recompiling the boot code sequence.
The early POST phase 10 checks the BIST result to determine if an error has occurred (decision block 24). If an error is detected (decision block 24—“no” leg), the early POST phase 10 records the error (e.g. in a nonvolatile memory such as the complementary metal-oxide-semiconductor (CMOS) random access memory (RAM) included in PC systems) (block 26) and the computer system may power down (block 28). If no error is detected (decision block 24—“yes” leg), the early POST phase provides another OEM hook (block 30). The early POST phase 10 continues with code to implement any workarounds or bug patches that may be required for the integrated circuits and other devices in the system (block 32). The early POST register initializations are then performed (block 34). That is, block 34 represents the code that initializes the registers in the various integrated circuits to the values required for normal operation of the integrated circuits (for those initializations performed in the early POST phase 10). The initializations performed in the block 34 are generated by the BIOS vendor, via human interpretation of the specification information provided by the integrated circuit vendor(s). The early POST phase 10 then performs memory configuration and test on the memory system in the computer system (block 36). If the memory test indicates that the memory is functioning normally (decision block 38—“yes” leg), the memory system is enabled and the early POST phase 10 is complete. On the other hand, if the memory test indicates that the memory is not functioning normally (decision block 38—“no” leg), the early POST phase 10 powers down the computer system (block 40). The reason for power down may be recorded (e.g. in CMOS RAM).
FIG. 3 illustrates the middle POST phase 12. The remainder of the BIOS code may be stored in a nonvolatile memory in compressed form. The middle POST phase 12 decompresses the BIOS (block 42). For example, the decompressed BIOS may be stored in the memory system, since the memory system was enabled in the early POST phase 10. The middle POST phase 12 enables any caches in the system (e.g. caches in the processors, external caches, etc.) and establishes the stack in memory (block 44). The keyboard, mouse, and video devices coupled to the computer system are enabled (block 46). Additionally, PC systems typically include the Peripheral Component Interconnect (PCI) for interfacing to various input/output (I/O) devices. The middle POST phase 12 enumerates the PCI devices, per the PCI specification (block 50). Middle POST register initializations are then performed (block 52). That is, block 52 represents the code that initializes the registers in the various integrated circuits to the values required for normal operation of the integrated circuits (for those initializations performed in the middle POST phase 12). The initializations performed in the block 52 are generated by the BIOS vendor, via human interpretation of the specification information provided by the integrated circuit vendor(s). Another OEM hook is provided (block 54), and the middle POST phase 12 is complete.
FIG. 4 illustrates the late POST phase 14. The computer system may include various setup options specific to the particular system. The late POST phase 14 reads the setup options (block 56). Late POST register initializations are then performed (block 58). That is, block 58 represents the code that initializes the registers in the various integrated circuits to the values required for normal operation of the integrated circuits (for those initializations performed in the late POST phase 14). The initializations in block 58 may include custom initializations indicated by the setup options. The initializations performed in the block 34 are generated by the BIOS vendor, via human interpretation of the specification information provided by the integrated circuit vendor(s). Another OEM hook is provided (block 60), and the late POST phase 14 is complete.
Typically, most of the register initializations for the integrated circuits in the computer system are performed in the early POST phase 10. Some initializations occur in the middle and late POST phases 12 and 14 as well. Additionally, in some cases, system-specific initializations may be performed in the middle and late POST phases 12 and 14. Generally, one of two methods are used for the register initializations: a hard-coded method and a table-driven method. Each method is described briefly below.
In the hard-coded method, the address of the register and/or the value to be written into the register is hard-coded into the code sequence. If the boot code sequence is compiled, the address and/or value may be represented by labels which are assigned a value in the source file. This method is often used for workarounds and bug fixes (e.g. block 32 in FIG. 2). Updating the hard-coded initializations is difficult and time consuming, as each line of code that performs register initializations must be located, examined, and updated by a human.
In the table-driven method, a data table is provided for each integrated circuit in the boot code sequence. Each entry in the table defines a register and the value to be programmed into the register. Typically, the value includes a mask (defining which bits of the register to update) and a data value. The current value of the register may be read and masked. The data value may be logically ORed into the masked current value, and the result written back to the register. The boot code sequence includes a routine (e.g. a loop) that reads each entry in the table and performs the initialization until the end of the table is reached. Updating the table-driven initializations may be simpler, since the data tables are a central location for possible updates. Unfortunately, various BIOS vendors (see below) use different formats for the data tables.
An algorithmic method is sometimes used during hardware initialization as well. Typically, the algorithmic method is used to perform a more complex task such as the memory test and configuration or the PCI enumeration. This method is often dependent not just on the integrated circuits included in the system, but also on the system configuration as a whole.
As mentioned above, there may be frequent updates to the initialization requirements for a given integrated circuit. Unfortunately, the updated initialization requirements are often not implemented properly. The frequency of updated information may be a source of error, since a BIOS vendor may fail to implement one of many updates. Furthermore, the updates are generally performed by humans interpreting the specification documents, checking the BIOS code for the locations that require change to implement the updates. Human error in locating all the locations, or in properly implementing the changes, is another source of error. Each of the various BIOS vendors implement a different software architecture for implementing the POST code described above, and differences in architecture may affect the proper implementation of updates. That is, updates may be performed in different fashions dependent on the architecture of the BIOS code. Furthermore, the number of independent updaters may be a source of error (e.g. each BIOS vendor must make updates, and some OEMs may have to make updates as well). While some updaters may make the updates properly, others may not.